Sep 7, 2026
For years, advances in AI computing have been driven by increasingly powerful processors. But as processor performance and power consumption continue to rise, the infrastructure surrounding the processor is becoming just as important as the silicon itself. One of the critical challenges sits in the "last inch" of the power chain, i.e. the final stage of power delivery before power reaches the processor.
Modern AI processors combine core voltages under 1 V with power demands running from hundreds of watts into the kilowatt domain. Delivering that much power at such a low voltage drives current dramatically higher, from hundreds of amperes toward the kiloampere range. At that scale, even very small amounts of resistance become significant sources of power loss and heat. Increasing AI performance is therefore no longer only about designing more powerful processors; it is also about delivering enough power to them efficiently.
In conventional power-delivery architectures, high current must travel laterally across the board to reach the processor. Resistance along this path creates conduction losses, dissipating energy as heat and reducing the amount of useful power delivered to the processor.
At the same time, AI workloads can change their power requirements extremely quickly, making the electrical characteristics of the power-delivery path increasingly important for maintaining a stable supply during sudden compute spikes. At kiloampere-class currents, adding more copper, regulator phases, or capacitors does not eliminate the resistance, inductance, and transient-response challenges of the final high-current path. The challenge is therefore no longer simply how to optimize individual components, but how the power-delivery architecture itself is designed.
A more powerful processor only provides value if the surrounding system can supply its power efficiently and manage the resulting heat. Losses in the power-delivery network reduce overall efficiency while adding to the thermal load the system must manage. The last inch therefore connects several of the industry's biggest challenges: power delivery, thermal management, physical space, and ultimately the amount of computing performance that can be achieved within a given footprint.
This is why compute per watt and compute density are becoming increasingly important alongside processor performance. A more efficient final stage means less power is lost as heat before it ever reaches the processor, cutting the heat burden elsewhere in the system. At data-center scale, these improvements contribute to greater compute density and lower cooling demand by making more effective use of the available power and physical footprint.
Solving the last inch requires shortening the distance that the highest current has to travel. This is driving the industry toward architectures that bring the final power conversion stage closer to the processor, including Vertical Power Delivery (VPD), where power can be delivered from beneath the processor rather than across the board.
At Lotus Microsystems, this principle is central to our approach to next-generation AI power delivery. Our vStrata™ platform uses silicon Power Interposer Technology to move that final conversion stage right up against the processor, addressing the electrical, thermal, and mechanical constraints created by increasingly dense AI systems.
The broader shift, however, goes beyond any individual power converter or architecture. Power delivery can no longer be treated as infrastructure that is designed only after the processor architecture has been defined. As current and power density continue to increase, the processor, power-delivery network, thermal infrastructure, and package increasingly need to be considered as one system.
The next major gains in AI computing will not come from processor innovation alone. They will also come from solving the infrastructure immediately around the processor and treating the last inch as a critical innovation bottleneck.
